1. Field of the Invention
The present invention relates generally to silicon-on-insulator (SOI) semiconductor devices; more particularly, the invention relates to a method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL).
2. Description of the Prior Art
Silicon-on-insulator (SOI) technology, which is becoming increasingly important in the field of integrated circuits, relates to the formation of transistors in a layer of semiconductor material which overlies an insulating layer. Fabricating integrated circuit (IC) devices in a thin SOI layer, as opposed to fabricating the same IC devices in a much thicker bulk silicon structure, allows for lower parasitic capacitance and for greater channel currents which, in turn, allows for faster speeds. Furthermore, field effect transistors such as MOSFETs fabricated in the silicon film of an SOI structure have many advantages over MOSFETs fabricated on the traditional bulk silicon substrates including resistance to short-channel effect, steeper subthreshold slopes, increased current drive, higher packing density, reduced parasitic capacitance, and simpler processing steps. In addition, recent advancements in the SOI silicon film quality, buried oxide quality, and manufacturing throughput have opened the door to a multitude of ultra large scale integration (ULSI) applications. Since SOI structures significantly alleviate the parasitic elements and increase the junction breakdown tolerance of the structure, the SOI technology is well-suited for high performance and high density integrated circuits.
MOSFETs fabricated with SOI technology include non-fully depleted MOSFETs with silicon film thickness greater than the maximum channel depletion width and fully-depleted MOSFETs having silicon film thickness less than the maximum channel depletion width. Fully-depleted SOI MOSFETs are known to have a near-ideal subthreshold slope. A slope factor of 1.05, a subthreshold slope of 63 mV/decade is indeed expected, but the presence of a grounded back gate brings it up to values around 66-68 mV/decade. According to the publication xe2x80x9cMonte Carlo Simulation of a 30 nm Dual-Gate MOSFET: How Short Can Si go?xe2x80x9d by D. J. Frank, S. E. Laux, and N. V. Fischetti, Technical Digest of IEDM, p. 553, 1992, the xe2x80x9cultimate MOSFETxe2x80x9d should be a fully-depleted MOSFET with dual (top and bottom) gates. In dual-gate SOI MOSFETs, values very close to the theoretical limit of 60 mV/decade are expected. Furthermore, this low value can be obtained for very short channel lengths provided that the gate oxide thickness and the silicon film thickness are scaled appropriately. Accordingly, the ultimate silicon device is a dual-gate SOI MOSFET with a gate length of 30 nm, an oxide thickness of 3 nm, and a silicon film thickness of 5 to 20 nm. Such a (simulated) device shows no short-channel effects for gate lengths larger than 70 nm and provides transconductance values up to 2300 mS/mm. Typically, short-channel effects in MOSFETs arise from electric-field lines that originate at the drain region and terminate on the channel region. The high-drain bias then induces source-side barrier lowering which, in turn, increases the off-state leakage current of the device. Thus, the fully-depleted dual-gate SOI MOSFETs are theoretically the xe2x80x9cultimate MOSFETsxe2x80x9d for avoiding punchthrough and short-channel effects in the deep-submicron region, for optimizing the control of the channel region by the gate, for obtaining the best possible subthreshold slope, and for maximizing the drain saturation current.
Nonetheless, the fabrication of a dual-gate or double-gate device is very difficult, and no satisfactory process technique has been found yet. According to the publication xe2x80x9cFully Depleted Dual-Gated Thin-Film SOI P-MOSFETs Fabricated in SOI Islands with an Isolated Buried Polysilicon Back Gatexe2x80x9d by J. P. Denton and G. W. Neudeck, IEEE Electron Device Letters, 17, p. 509, 1996, dual-gate SOI transistors can be fabricated using epitaxial lateral overgrowth (ELO) or tunnel epitaxy of silicon over an oxidized polysilicon gate. A second gate is then fabricated on top of the device. Another fabrication method disclosed in xe2x80x9cSilicon-on-Insulator Gate-All-Around Devicexe2x80x9d by J. P. Colinge, M. H. Gao, A. Romano, H. Maes, and C. Claeys, Technical Digest of IEDM, p. 595, 1990 makes use of regular xe2x80x9cseparation by implanted oxygen (SIMOX)xe2x80x9d wafers and adopts a process sequence which is similar to that used for regular SOI MOSFET fabrication, with only one additional mask step and a wet-etch step. The device is called the Gate-All-Around (GAA) MOSFET and was first proposed in 1990. However, the problem with these structures is that the two gates are not self-aligned and that they have poor scaling characteristics.
The next best thing to a double-gate SOI MOSFET is a single-gate device with an implanted ground plane under the buried oxide so as to increases the impurity concentration of the implanted ground plane underneath the channel region of the device to be higher than that of the substrate. The implanted ground plane prevents the electric field lines originating at the drain from spreading under the channel region and from acting as a virtual, positively-biased back gate which would create drain-induced barrier lowering (DIBL) and other short-channel effects. On the other hand, the drawback of an implanted ground plane that would extend underneath the entire device is the increase of the parasitic capacitance between the source/drain and the substrate.
Therefore, it is an object of the present invention to provide a method of fabricating a silicon-on-insulator (SOI) semiconductor device with an implanted ground plane in which the doping concentration within the underlying silicon substrate is increased underneath the channel region but not under the source and drain regions nor underneath the isolation region between devices so that the source-side barrier is shielded from the high drain-bias to suppress the short-channel effects. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs. For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential).
According to an embodiment of the present invention, a SOI semiconductor device with an implanted ground plane that is self-aligned to be located underneath a channel region of the semiconductor device but not extending to be underneath the source and the drain is fabricated, comprising the steps of:
(a) forming a semiconductor layer on a semiconductor substrate via a first insulation layer;
(b) forming a sacrificial layer on the semiconductor layer;
(c) forming a window in the sacrificial layer corresponding to the location of a gate electrode to be formed;
(d) forming a high-concentration impurity region in said semiconductor substrate, by implanting ions of the same conductivity type as the semiconductor substrate through the window in the sacrificial layer, an impurity concentration of said impurity region being higher than that of said semiconductor substrate;
(e) forming a gate electrode within said window;
(f) removing said sacrificial layer; and
(g) forming source and drain regions in said semiconductor layer by implanting doping ions whose conductivity type is opposite to that of the semiconductor substrate, using said gate electrode as a mask.
According to another embodiment of the present invention, a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS is fabricated, wherein the CMOS is comprised of two SOI-type MOSFET semiconductor devices of opposite conductivity types formed on a same semiconductor substrate. Since there is a basic inconsistency in forming two MOSFET devices of opposite conductivity types on a same semiconductor substrate, a well region whose conductivity type is opposite to that of the semiconductor substrate is formed in the semiconductor substrate by a deep ionic implantation. For example, a region having boron ions injected thereto becomes a P-well region, and a region having phosphorous ions injected thereto becomes a N-well region. Subsequently, two ground planes of opposite conductivity types are each implanted underneath a corresponding channel region of the CMOS by implanting doping ions of higher impurity concentration into the semiconductor substrate and the well region, respectively. Wherein, doping ions having the same conductivity type as the substrate are implanted into the substrate, and doping ions having the same conductivity type as the well region are implanted into the well region.
Hence, an SOI CMOS semiconductor device with a P+ ground plane underneath the N-channel device and a N+ ground plane underneath the P-channel device is fabricated according to the present invention. If a P-type semiconductor substrate is used, the implanted P+ ground plane is connected to ground and the implanted N+ ground plane is connected to VDD (supply voltage). This necessitates the formation of a N-well underneath the P-channel devices and a well contact. The N-well can be formed by deep phosphorous implantation through the P-channel devices. On the other hand, if a N-type semiconductor substrate is used, the implanted N+ ground plane is connected to ground and the implanted P+ ground plane is connected to VDD (supply voltage). This necessitates the formation of a P-well underneath the N-channel devices. The P-well can be formed by deep boron implantation through the N-channel devices. The layout of the SOI CMOS device according to the present invention resembles that of a bulk CMOS device except for the self-aligned implanted ground planes underneath the corresponding channel regions. Thereby, the implanted ground plane according to the present invention prevents the electric field lines from the gate electrode from terminating under the channel region, which in turn decreases the short channel effects.